This invention relates to a type of dynamic random-access memory (dynamic RAM, or DRAM) that is written and read in high-speed bursts synchronized with a clock signal. This novel type of memory will be referred to below as a synchronous burst-access memory.
A synchronous burst-access memory can be compared to the well-known dual-port random-access memory (dual-port RAM). A dual-port RAM basically comprises an array of DRAM memory cells and a data register. The memory cells can be accessed "at random" by latching a row address, then a column address, and reading or writing the bit or bits located at the intersection of the row and column. Alternatively, an entire row of bits can be transferred at once to the data register, then read serially in synchronization with a clock signal. Some dual-port RAMs enable data to be written serially as well as read. Serial and random access can be carried out simultaneously, and serial access can be performed at high speed.
Dual-port RAM has often been used to store image data which are read serially to generate a video signal for a raster-scan display. More recently, dual-port RAM has been used in systems employing processors of the reduced instruction-set type (so-called RISC processors), which run at high speeds and often require access to a series of bits.
A drawback of dual-port RAM is that complex on-chip circuitry is required to control two ports simultaneously. This leads to chip sizes 40% to 50% larger than general-purpose DRAM, and increases the cost of manufacturing and testing the chip.
Another drawback is that the control and address signals supplied to dual-port RAM have stringent and interrelated setup, hold, and other timing requirements, which are not easily satisfied at high operating speeds. This problem is particularly acute when the same control signals are supplied to a plurality of memory devices on a printed circuit board. Board design becomes difficult and powerful signal drivers become necessary; but these drivers generate unwanted electrical noise that can cause other devices on the board to malfunction.
Timing would be easier if all control and address signals were synchronized to a single clock signal, but existing dual-port RAM devices make no provision for this type of synchronization; the clock signal is used only to synchronize serial data output, or serial input and output. Synchronous static RAM devices are known, but their synchronization schemes are not directly applicable to dynamic RAM because row and column addresses are multiplexed in dynamic RAM, whereas they are not multiplexed in static RAM. In addition, if existing static RAM synchronization schemes were to be applied to dynamic RAM, operations such as row address decoding would not begin until after input of the synchronizing clock edge, which would lead to delays inappropriate for a burst-access device.